High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications by Weitao Li Fule Li & Zhihua Wang

Author:Weitao Li, Fule Li & Zhihua Wang
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

(4.7)

That is

(4.8)

With the compressed reference voltage, , the tolerated sampling noise is reduced and hence the sampling capacitor must be enlarged, increasing the load of the previous stage.

Considering a second stage following a 2.5-bit stage, the sampling capacitance in the first stage is and the sampling capacitance in the second stage is . If the interstage gain of the first stage is 4, like that in Fig. 4.6a, is . If the interstage gain of the first stage is reduced to 2, increases to . For the first 2.5-bit stage, the larger load will increase the opamp’s current. From the point of view of the opamp noise, similar to Eq. 4.8, the tolerated noise in the second stage is also compressed and hence the opamp power dissipation increases.

To sum up, the range scaling relaxes the requirement of the opamp’s output swing. On the other hand, the increased load and the extra current compensating for the strict opamp noise requirement in the following stages should be considered.

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